diff -ur xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/newmmio.h xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/newmmio.h
--- xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/newmmio.h	Sat Feb  7 11:05:30 1998
+++ xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/newmmio.h	Thu May 25 18:23:41 2000
@@ -248,7 +248,7 @@
 #define WaitQueue(v)					\
 	if(!s3PCIRetry) {				\
 	   mem_barrier();				\
-	   while(inb(GP_STAT) & (0x0100 >> (v)));	\
+	   while(mmio_INB_GP_STAT() & (0x0100 >> (v)));	\
 	}
 
 #define CMD_REG_WIDTH  0x200  	/* select 32bit command register */
diff -ur xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3.h xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3.h
--- xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3.h	Mon Oct 19 22:41:26 1998
+++ xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3.h	Wed Jun 14 15:32:08 2000
@@ -133,7 +133,9 @@
 extern unsigned char s3InTi3026IndReg(unsigned char);
 extern void s3OutTiIndReg(unsigned char, unsigned char, unsigned char);
 extern unsigned char s3InTiIndReg(unsigned char);
-  
+
+extern void S3AccelSetup();
+extern void S3AccelSetup_NewMMIO();
 
 
 extern vgaVideoChipRec s3InfoRec;
diff -ur xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3accel.c xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3accel.c
--- xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3accel.c	Sat Oct 24 09:55:01 1998
+++ xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3accel.c	Wed Jun 14 15:37:11 2000
@@ -209,6 +209,23 @@
 
 }
 
+
+void
+#ifdef S3_NEWMMIO
+S3AccelSetup_NewMMIO() 
+#else
+S3AccelSetup() 
+#endif
+{
+  WaitQueue(5);
+  SET_SCISSORS(0,0,s3ScissR,s3ScissB);
+  if(s3Bpp > 2) {
+    if(s3newmmio)
+      SET_MULT_MISC(0x200);
+    else 
+      SET_MULT_MISC(0);
+  }
+}
 		/******************\
 		|	Sync	   |
 		\******************/
diff -ur xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3init.c xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3init.c
--- xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3init.c	Sat Dec 11 18:32:06 1999
+++ xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3init.c	Sun Jul 16 20:36:37 2000
@@ -225,6 +225,8 @@
 					/* disabled anyway */
 
 /* !! double negative? (MArk) */
+/* !! is used to guarantee that right hand operand of (binary) xor "^" 
+   really is a boolean 0/1 value (and not e.g. some bit mask)  (Harald) */
    if ((S3_TRIO64V_SERIES(s3ChipId) && (s3ChipRev <= 0x53) && (s3Bpp==1)) ^
        !!OFLG_ISSET(OPTION_TRIO64VP_BUG2, &vga256InfoRec.options)) {
       /* set correct blanking for broken Trio64V+ to avoid bright left border:
@@ -968,6 +970,20 @@
    outb(DAC_MASK, 0x00);
 
  /* Reset the 8514/A, and disable all interrupts. */
+
+   /* 
+    * XXX: resetting the Trio64V2/GX causes trouble with the SGRAM memory bus
+    * (gets out of sync?  same as setting CR88_6) which I don't know to fix,
+    * so better not reset that chip and cross fingers... 
+    * This happens at least for some IBM Netfinity boxes (e.g. 7000M10) with 1MB SGRAM.
+    */
+   if (S3_TRIO64V2_SERIES(s3ChipId)) {
+     outb(vgaCRIndex, 0x36);
+     tmp = inb(vgaCRReg);
+     if ((tmp & 0x0c) != 0x04) /* no SGRAM */
+       outw(SUBSYS_CNTL, GPCTRL_RESET | CHPTEST_NORMAL);
+   }
+   else /* do normal reset for S3 chip... */
    outw(SUBSYS_CNTL, GPCTRL_RESET | CHPTEST_NORMAL);
    outw(SUBSYS_CNTL, GPCTRL_ENAB | CHPTEST_NORMAL);
 
@@ -997,14 +1013,10 @@
 	outb(vgaCRReg, s3SAM256);
    }
 
-   WaitQueue(5);
-   SET_SCISSORS(0,0,s3ScissR,s3ScissB);
-   if(s3Bpp > 2) {
-	if(s3newmmio)
-      	  SET_MULT_MISC(0x200);
-	else 
-      	  SET_MULT_MISC(0);
-    }
+   if (s3newmmio)
+     S3AccelSetup_NewMMIO();
+   else 
+     S3AccelSetup();
 
    return TRUE;
 }
diff -ur xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3ramdacs.c xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3ramdacs.c
--- xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3ramdacs.c	Mon Oct 19 22:41:27 1998
+++ xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3ramdacs.c	Sun Jul 16 20:14:50 2000
@@ -2741,7 +2741,7 @@
 
       /* for Trio64+ we need corrected blank signal timing */
       if (!(S3_TRIO64V_SERIES(s3ChipId) && (s3ChipRev <= 0x53)
-	    || (S3_TRIO64V2_SERIES(s3ChipId))) ^ 
+	    /* || (S3_TRIO64V2_SERIES(s3ChipId)) */ ) ^ 
 	  !!OFLG_ISSET(OPTION_TRIO64VP_BUG1, &vga256InfoRec.options)) {
 	 cr33 |= 0x20;
       }
diff -ur xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3reg.h xc/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3reg.h
--- xc336/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3reg.h	Sat Feb  7 11:05:45 1998
+++ xc3/programs/Xserver/hw/xfree86/vga256/drivers/s3_svga/s3reg.h	Wed Jun 14 15:19:34 2000
@@ -441,10 +441,23 @@
      unsigned char r, g, b;
 } LUTENTRY;
 
+/*
+ * mmio reads from GP_STAT
+ */
+#if !defined(__alpha__)
+#define mmio_INB_GP_STAT() 	(*(((volatile unsigned char*)s3MmioMem)+GP_STAT) & 0xff)
+#define mmio_INW_GP_STAT() 	(*(((volatile unsigned short*)s3MmioMem)+GP_STAT/2))
+#else
+#define mmio_INB_GP_STAT() 	inb(GP_STAT)
+#define mmio_INW_GP_STAT() 	inw(GP_STAT)
+#endif
 
 #define WaitIdle() 	do {  		\
 	mem_barrier(); 			\
-	while(inw(GP_STAT) & GPBUSY); 	\
+	if (s3newmmio) 			\
+	    while(mmio_INW_GP_STAT() & GPBUSY); 	\
+	else 				\
+	    while(inw(GP_STAT) & GPBUSY); 	\
 } while(0)
 
 
@@ -466,7 +479,10 @@
 #else
    #define WaitQueue(v)   do {  		\
 	mem_barrier(); 				\
-	while(inb(GP_STAT) & (0x0100 >> (v))); 	\
+	if (s3newmmio) 			\
+	   while(mmio_INB_GP_STAT() & (0x0100 >> (v))); 	\
+	else 				\
+	   while(inb(GP_STAT) & (0x0100 >> (v))); 	\
    } while (0)
 
    #define CMD_REG_WIDTH  0  	/* select 16bit command register */