PIC18F4220 |
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CONFIG1H (address:0x300001, mask:0xCF) |
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OSC -- Oscillator Selection bits |
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OSC = LP |
0xF0 |
LP Oscillator. |
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OSC = XT |
0xF1 |
XT Oscillator. |
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OSC = HS |
0xF2 |
HS Oscillator. |
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OSC = EC |
0xF4 |
EC oscillator, CLKO function on RA6. |
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OSC = ECIO |
0xF5 |
EC oscillator, port function on RA6. |
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OSC = HSPLL |
0xF6 |
HS oscillator, PLL enabled (clock frequency = 4 x FOSC1). |
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OSC = RCIO |
0xF7 |
External RC oscillator, port function on RA6. |
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OSC = INTIO2 |
0xF8 |
Internal RC oscillator, port function on RA6 and port function on RA7. |
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OSC = INTIO1 |
0xF9 |
Internal RC oscillator, CLKO function on RA6 and port function on RA7. |
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OSC = RC |
0xFC |
External RC oscillator, CLKO function on RA6. |
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FSCM -- Fail-Safe Clock Monitor Enable bit |
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FSCM = OFF |
0xBF |
Fail-Safe Clock Monitor disabled. |
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FSCM = ON |
0xFF |
Fail-Safe Clock Monitor enabled. |
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IESO -- Internal/External Switchover bit |
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IESO = OFF |
0x7F |
Internal/External Switchover mode disabled. |
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IESO = ON |
0xFF |
Internal/External Switchover mode enabled. |
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CONFIG2L (address:0x300002, mask:0x0F) |
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PWRT -- Power-up Timer enable bit |
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PWRT = ON |
0xFE |
PWRT enabled. |
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PWRT = OFF |
0xFF |
PWRT disabled. |
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BOR -- Brown-out Reset enable bit |
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BOR = OFF |
0xFD |
Brown-out Reset disabled. |
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BOR = ON |
0xFF |
Brown-out Reset enabled. |
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BORV -- Brown-out Reset Voltage bits |
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BORV = 45 |
0xF3 |
VBOR set to 4.5V. |
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BORV = 42 |
0xF7 |
VBOR set to 4.2V. |
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BORV = 27 |
0xFB |
VBOR set to 2.7V. |
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BORV = 20 |
0xFF |
VBOR set to 2.0V. |
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CONFIG2H (address:0x300003, mask:0x1F) |
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WDT -- Watchdog Timer Enable bit |
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WDT = OFF |
0xFE |
WDT disabled (control is placed on the SWDTEN bit). |
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WDT = ON |
0xFF |
WDT enabled. |
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WDTPS -- Watchdog Timer Postscale Select bits |
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WDTPS = 1 |
0xE1 |
1:1. |
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WDTPS = 2 |
0xE3 |
1:2. |
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WDTPS = 4 |
0xE5 |
1:4. |
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WDTPS = 8 |
0xE7 |
1:8. |
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WDTPS = 16 |
0xE9 |
1:16. |
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WDTPS = 32 |
0xEB |
1:32. |
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WDTPS = 64 |
0xED |
1:64. |
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WDTPS = 128 |
0xEF |
1:128. |
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WDTPS = 256 |
0xF1 |
1:256. |
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WDTPS = 512 |
0xF3 |
1:512. |
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WDTPS = 1024 |
0xF5 |
1:1024. |
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WDTPS = 2048 |
0xF7 |
1:2048. |
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WDTPS = 4096 |
0xF9 |
1:4096. |
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WDTPS = 8192 |
0xFB |
1:8192. |
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WDTPS = 16384 |
0xFD |
1:16384. |
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WDTPS = 32768 |
0xFF |
1:32768. |
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CONFIG3H (address:0x300005, mask:0x83) |
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CCP2MX -- CCP2 MUX bit |
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CCP2MX = OFF |
0xFE |
CCP2 input/output is multiplexed with RB3. |
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CCP2MX = ON |
0xFF |
CCP2 input/output is multiplexed with RC1. |
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PBAD -- PORTB A/D Enable bit |
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PBAD = DIG |
0xFD |
PORTB<4:0> pins are configured as digital I/O on Reset. |
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PBAD = ANA |
0xFF |
PORTB<4:0> pins are configured as analog input channels on Reset. |
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MCLRE -- MCLR Pin Enable bit |
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MCLRE = OFF |
0x7F |
MCLR disabled; RE3 input is enabled in 40-pin devices only (PIC18F4X20). |
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MCLRE = ON |
0xFF |
MCLR pin enabled; RE3 input pin disabled. |
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CONFIG4L (address:0x300006, mask:0x85) |
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STVR -- Stack Full/Underflow Reset Enable bit |
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STVR = OFF |
0xFE |
Stack full/underflow will not cause Reset. |
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STVR = ON |
0xFF |
Stack full/underflow will cause Reset. |
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LVP -- Single-Supply ICSP Enable bit |
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LVP = OFF |
0xFB |
Single-Supply ICSP disabled. |
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LVP = ON |
0xFF |
Single-Supply ICSP enabled. |
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DEBUG -- Background Debugger Enable bit |
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DEBUG = ON |
0x7F |
Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug. |
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DEBUG = OFF |
0xFF |
Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins. |
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CONFIG5L (address:0x300008, mask:0x0F) |
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CP0 -- Code Protection bit |
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CP0 = ON |
0xFE |
Block 0 (000200-0007FFh) code-protected. |
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CP0 = OFF |
0xFF |
Block 0 (000200-0007FFh) not code-protected. |
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CP1 -- Code Protection bit |
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CP1 = ON |
0xFD |
Block 1 (000800-000FFFh) code-protected. |
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CP1 = OFF |
0xFF |
Block 1 (000800-000FFFh) not code-protected. |
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CONFIG5H (address:0x300009, mask:0xC0) |
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CPB -- Boot Block Code Protection bit |
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CPB = ON |
0xBF |
Boot block (000000-0001FFh) is code-protected. |
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CPB = OFF |
0xFF |
Boot block (000000-0001FFh) is not code-protected. |
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CPD -- Data EEPROM Code Protection bit |
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CPD = ON |
0x7F |
Data EEPROM is code-protected. |
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CPD = OFF |
0xFF |
Data EEPROM is not code-protected. |
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CONFIG6L (address:0x30000A, mask:0x0F) |
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WRT0 -- Write Protection bit |
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WRT0 = ON |
0xFE |
Block 0 (000200-0007FFh) write-protected. |
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WRT0 = OFF |
0xFF |
Block 0 (000200-0007FFh) not write-protected. |
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WRT1 -- Write Protection bit |
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WRT1 = ON |
0xFD |
Block 1 (000800-000FFFh) write-protected. |
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WRT1 = OFF |
0xFF |
Block 1 (000800-000FFFh) not write-protected. |
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CONFIG6H (address:0x30000B, mask:0xE0) |
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WRTC -- Configuration Register Write Protection bit |
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WRTC = ON |
0xDF |
Configuration registers (300000-3000FFh) are write-protected. |
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WRTC = OFF |
0xFF |
Configuration registers (300000-3000FFh) are not write-protected. |
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WRTB -- Boot Block Write Protection bit |
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WRTB = ON |
0xBF |
Boot block (000000-0001FFh) is write-protected. |
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WRTB = OFF |
0xFF |
Boot block (000000-0001FFh) is not write-protected. |
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WRTD -- Data EEPROM Write Protection bit |
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WRTD = ON |
0x7F |
Data EEPROM is write-protected. |
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WRTD = OFF |
0xFF |
Data EEPROM is not write-protected. |
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CONFIG7L (address:0x30000C, mask:0x0F) |
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EBTR0 -- Table Read Protection bit |
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EBTR0 = ON |
0xFE |
Block 0 (000200-0007FFh) protected from table reads executed in other blocks. |
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EBTR0 = OFF |
0xFF |
Block 0 (000200-0007FFh) not protected from table reads executed in other blocks. |
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EBTR1 -- Table Read Protection bit |
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EBTR1 = ON |
0xFD |
Block 1 (000800-000FFFh) protected from table reads executed in other blocks. |
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EBTR1 = OFF |
0xFF |
Block 1 (000800-000FFFh) not protected from table reads executed in other blocks. |
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CONFIG7H (address:0x30000D, mask:0x40) |
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EBTRB -- Boot Block Table Read Protection bit |
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EBTRB = ON |
0xBF |
Boot block (000000-0001FFh) is protected from table reads executed in other blocks. |
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EBTRB = OFF |
0xFF |
Boot block (000000-0001FFh) is not protected from table reads executed in other blocks. |
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