PIC18F86J93 |
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CONFIG1L (address:0x00FFF8, mask:0xE1) |
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WDTEN -- Watchdog Timer |
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WDTEN = OFF |
0xFE |
Disabled-Controlled by SWDTEN bit. |
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WDTEN = ON |
0xFF |
Enabled. |
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STVREN -- Stack Overflow Reset |
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STVREN = OFF |
0xDF |
Disabled. |
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STVREN = ON |
0xFF |
Enabled. |
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XINST -- Extended Instruction Set Enable bit |
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XINST = OFF |
0xBF |
Disabled. |
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XINST = ON |
0xFF |
Enabled. |
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CONFIG1H (address:0x00FFF9, mask:0xF4) |
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CP0 -- Code Protect |
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CP0 = ON |
0xFB |
Enabled. |
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CP0 = OFF |
0xFF |
Disabled. |
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CONFIG2L (address:0x00FFFA, mask:0xDF) |
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OSC -- Oscillator Selection bits |
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OSC = INTOSC |
0xF8 |
Internal oscillator, port function on RA6 and RA7 . |
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OSC = INTOSCPLL |
0xF9 |
INTOSC with PLL enabled, port function on RA6 and RA7. |
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OSC = INTOSCO |
0xFA |
Internal oscillator, CLKOUT on RA6 and port function on RA7. |
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OSC = INTOSCPLLO |
0xFB |
INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7. |
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OSC = HS |
0xFC |
HS oscillator. |
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OSC = HSPLL |
0xFD |
HS oscillator, PLL enabled. |
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OSC = EC |
0xFE |
EC Oscillator with clock out on RA6. |
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OSC = ECPLL |
0xFF |
EC Oscillator with PLL. |
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T1DIG -- Secondary Clock Source T1OSCEN Enforcement |
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T1DIG = OFF |
0xF7 |
Secondary Oscillator clock source may not be selected. |
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T1DIG = ON |
0xFF |
Secondary Oscillator clock source may be selected. |
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LPT1OSC -- Low-Power Timer1 Oscillator Enable bit |
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LPT1OSC = ON |
0xEF |
Timer1 oscillator configured for low-power operation. |
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LPT1OSC = OFF |
0xFF |
Timer1 oscillator configured for higher power operation. |
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FCMEN -- Fail-Safe Clock Monitor Enable bit |
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FCMEN = OFF |
0xBF |
Fail-Safe Clock Monitor disabled. |
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FCMEN = ON |
0xFF |
Fail-Safe Clock Monitor enabled. |
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IESO -- Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit |
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IESO = OFF |
0x7F |
Two-Speed Start-up disabled. |
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IESO = ON |
0xFF |
Two-Speed Start-up enabled. |
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CONFIG2H (address:0x00FFFB, mask:0xFF) |
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WDTPS -- Watchdog Timer Postscaler Select bits |
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WDTPS = 1 |
0xF0 |
1:1. |
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WDTPS = 2 |
0xF1 |
1:2. |
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WDTPS = 4 |
0xF2 |
1:4. |
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WDTPS = 8 |
0xF3 |
1:8. |
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WDTPS = 16 |
0xF4 |
1:16. |
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WDTPS = 32 |
0xF5 |
1:32. |
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WDTPS = 64 |
0xF6 |
1:64. |
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WDTPS = 128 |
0xF7 |
1:128. |
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WDTPS = 256 |
0xF8 |
1:256. |
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WDTPS = 512 |
0xF9 |
1:512. |
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WDTPS = 1024 |
0xFA |
1:1024. |
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WDTPS = 2048 |
0xFB |
1:2048. |
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WDTPS = 4096 |
0xFC |
1:4096. |
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WDTPS = 8192 |
0xFD |
1:8192. |
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WDTPS = 16384 |
0xFE |
1:16384. |
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WDTPS = 32768 |
0xFF |
1:32768. |
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CONFIG3L (address:0x00FFFC, mask:0xF2) |
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RTCSOSC -- RTCC Reference Clock Select bit |
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RTCSOSC = INTOSCREF |
0xFD |
RTCC uses INTOSC/INTRC as reference clock. |
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RTCSOSC = T1OSCREF |
0xFF |
RTCC uses T1OSC/T1CKI as reference clock. |
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CONFIG3H (address:0x00FFFD, mask:0xF1) |
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CCP2MX -- CCP2 MUX |
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CCP2MX = ALTERNATE |
0xFE |
RE7. |
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CCP2MX = DEFAULT |
0xFF |
RC1. |
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