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±â´Éº° Instruction ºÐ·ù

1.
Memory Integer Load/Store Summary

Mnemonic Operation
LDA Load Address
LDAH Load Address High
LDBU Load Zero-Extended Byte from Memory to Register
LDL Load Sign-Extended Longword
LDL_L Load Sign-Extended Longword Locked
LDQ Load Quadword
LDQ_L Load Quadword Locked
LDQ_U Load Quadword Unaligned
LDWU Load Zero-Extended Word from Memory to Register
STB Store Byte
STL Store Longword
STL_C Store Longword Conditional
STQ Store Quadword
STQ_C Store Quadword Conditional
STQ_U Store Quadword Unaligned
STW Store Word

2.
Control Instructions Summary

Mnemonic Operation
BEQ Branch if Register Equal to Zero
BGE Branch if Register Greater Than or Equal to Zero
BGT Branch if Register Greater Than Zero
BLBC Branch if Register Low Bit Is Clear
BLBS Branch if Register Low Bit Is Set
BLE Branch if Register Less Than or Equal to Zero
BLT Branch if Register Less Than Zero

3.
Integer Arithmetic Instructions Summary

Mnemonic Operation
ADD Add Quadword/Longword
S4ADD Scaled Add by 4
S8ADD Scaled Add by 8
CMPEQ Compare Signed Quadword Equal
CMPLT Compare Signed Quadword Less Than
CMPLE Compare Signed Quadword Less Than or Equal
CTLZ Count leading zero
CTPOP Count population
CTTZ Count trailing zero
CMPULT Compare Unsigned Quadword Less Than
CMPULE Compare Unsigned Quadword Less Than or Equal
MUL Multiply Quadword/Longword
UMULH Multiply Quadword Unsigned High
SUB Subtract Quadword/Longword
S4SUB Scaled Subtract by 4
S8SUB Scaled Subtract by 8

4.
Logical and Shift Instructions Summary

Mnemonic Operation
AND Logical Product
BIC Logical Product with Complement
BIS Logical Sum (OR)
EQV Logical Equivalence (XORNOT)
ORNOT Logical Sum with Complement
XOR Logical Difference
CMOVxx Conditional Move Integer
SLL Shift Left Logical
SRA Shift Right Arithmetic
SRL Shift Right Logical

5.
Byte Manipulation Instructions

Mnemonic Operation
LDBU/LDWU Load byte/word unaligned
SEXTB/SEXTW Sign-extend byte/word
STB/STW Store byte/word

6.
Memory Floating-Point Instructions

Mnemonic Operation Subset
LDF Load F_floating VAX
LDG Load G_floating (Load D_floating) VAX
LDS Load S_floating (Load Longword Integer) Both
LDT Load T_floating (Load Quadword Integer) Both
STF Store F_floating VAX
STG Store G_floating (Store D_floating) VAX
STS Store S_floating (Store Longword Integer) Both
STT Store T_floating (Store Quadword Integer) Both

7.
Floating-Point Branch Instructions Summary

Mnemonic Operation Subset
FBEQ Floating Branch Equal Both
FBGE Floating Branch Greater Than or Equal Both
FBGT Floating Branch Greater Than Both
FBLE Floating Branch Less Than or Equal Both
FBLT Floating Branch Less Than Both
FBNE Floating Branch Not Equal Both

8.
Floating-Point Operate Instructions Summary

Mnemonic Operation Subset
CPYS Copy Sign Both
CPYSE Copy Sign and Exponent Both
CPYSN Copy Sign Negate Both
CVTLQ Convert Longword to Quadword Both
CVTQL Convert Quadword to Longword Both
FCMOVxx Floating Conditional Move Both
MF_FPCR Move from Floating-point Control Register Both
MT_FPCR Move to Floating-point Control Register Both
ADDF Add F_floating VAX
ADDG Add G_floating VAX
ADDS Add S_floating IEEE
ADDT Add T_floating IEEE
CMPGxx Compare G_floating VAX
CMPTxx Compare T_floating IEEE
CVTDG Convert D_floating to G_floating VAX
CVTGD Convert G_floating to D_floating VAX
CVTGF Convert G_floating to F_floating VAX
CVTGQ Convert G_floating to Quadword VAX
CVTQF Convert Quadword to F_floating VAX
CVTQG Convert Quadword to G_floating VAX
CVTQS Convert Quadword to S_floating IEEE
CVTQT Convert Quadword to T_floating IEEE
CVTST Convert S_floating to T_floating IEEE
CVTTQ Convert T_floating to Quadword IEEE
CVTTS Convert T_floating to S_floating IEEE
DIVF Divide F_floating VAX
DIVG Divide G_floating VAX
DIVS Divide S_floating IEEE
DIVT Divide T_floating IEEE
FTOIS Floating-point to integer register move, S_floating IEEE
FTOIT Floating-point to integer register move, T_floating IEEE
ITOFF Integer to floating-point register move, F_floating VAX
ITOFS Integer to floating-point register move, S_floating IEEE
ITOFT Integer to floating-point register move, T_floating IEEE
MULF Multiply F_floating VAX
MULG Multiply G_floating VAX
MULS Multiply S_floating IEEE
MULT Multiply T_floating IEEE
SQRTF Square root F_floating VAX
SQRTG Square root G_floating VAX
SQRTS Square root S_floating IEEE
SQRTT Square root T_floating IEEE
SUBF Subtract F_floating VAX
SUBG Subtract G_floating VAX
SUBS Subtract S_floating IEEE
SUBT Subtract T_floating IEEE

9.
Miscellaneous Instructions

Mnemonic Operation
AMASK Architecture Mask
CALL_PAL Call Privileged Architecture Library Routine
ECB Evict Cache Block
EXCB Exception Barrier
FETCH Prefetch Data
FETCH_M Prefetch Data, Modify Intent
IMPLVER Implementation Version
MB Memory Barrier
RPCC Read Processor Cycle Counter
TRAPB Trap Barrier
WH64 Write Hint - 64 Bytes
WMB Write Memory Barrier

10.
VAX Compatibility Instructions

Mnemonic Operation
RC Read and Clear
RS Read and Set

11.
Multimedia (Graphics and Video) Support

Mnemonic Operation
MINUB8 Vector Unsigned Byte Minimum
MINSB8 Vector Signed Byte Minimum
MINUW4 Vector Unsigned Word Minimum
MINSW4 Vector Signed Word Minimum
MAXUB8 Vector Unsigned Byte Maximum
MAXSB8 Vector Signed Byte Maximum
MAXUW4 Vector Unsigned Word Maximum
MAXSW4 Vector Signed Word Maximum
PERR Pixel Error
PKLB Pack Longwords to Bytes
PKWB Pack Words to Bytes
UNPKBL Unpack Bytes to Longwords
UNPKBW Unpack Bytes to Words


next up previous contents
Next: GAS¸¦ ÀÌ¿ëÇÑ Alpha Assembly Up: Alpha InstructionÀÇ ºÐ·ù Previous: Alpha InstructionÀÇ Á¾·ù
Kwon Soon Son
1998-11-25